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SIMD: the PIE vector unit

128-bit vector kernels with the inner loops written as GNAT inline assembly — vendored, experimental, and honest about it.

What it is

ESP32S3.SIMD exposes the S3's PIE SIMD extension — the Xtensa LX7's 128-bit q0–q7 registers — with the inner loops written as GNAT inline assembly (System.Machine_Code) inside Ada bodies.

Application code withs the facade; the per-type kernels live in children by element family:

procedure Add   (A, B : SIMD_F32_Vector; Result : in out SIMD_F32_Vector);
procedure Sub   (A, B : SIMD_F32_Vector; Result : in out SIMD_F32_Vector);
procedure Mul_Scalar (...);
procedure MAC   (...);
function  Sum         (A : SIMD_F32_Vector) return IEEE_Float_32;
function  Dot_Product (A, B : SIMD_F32_Vector) return IEEE_Float_32;
procedure Ceil  (A : SIMD_F32_Vector; Result : in out SIMD_F32_Vector; Max_Val : IEEE_Float_32);
procedure Floor (...);
procedure Neg / Abs_Val (...);

Contracts on these are intentionally explicit — the preconditions state the length and aliasing rules rather than leaving them to a comment.

Read this before you depend on it

Status: experimental / beta. Correctness is validated for a subset of operations through the benchmark harness; edge cases and operation interactions are not systematically exercised. The library's own README says not to rely on it in safety-critical contexts without independent verification, and repeating that here rather than quietly omitting it is the point.

Provenance: vendored from rowsail/ada-esp32-s3-simd, itself based on the low-level implementation ideas of the upstream zliu43/esp_simd project. It is not original work of this SDK, and the vendoring is recorded rather than blurred.

Enabling the coprocessor

PIE is coprocessor 3. The bare boot's start.S sets CPENABLE = 0x09 to enable it — so unlike most of the HAL, this library depends on a startup detail rather than only on its own registers. If you port the boot code, that bit has to come with it or every kernel faults.